Semiconductor wafers are widely used as substrates for integrated circuits (ICs). Cleaning of wafers must take place after most processing steps and before each high-temperature operation, making it the most frequently repeated step in IC manufacturing. Existing methods for ultra-clean wafer surface preparation fall into two broad categories: wet cleaning processes such as immersion and spray techniques, and dry cleaning processes such as chemical vapor and plasma based techniques. Wet cleaning techniques have been successfully used for the past thirty years and are still favored because many inherent properties of liquid solutions facilitate the removal of metals and particles. The wet cleaning processing typically consists of a series of steps of immersing or spraying the wafers with appropriate chemical solutions.
As critical dimensions decrease and the wafer size increases, there are always needs for new techniques and chemistry for cleaning and drying. Currently, the investigation has been driven by a multitude of processes, including new materials/substrates for high mobility channels, epitaxial SiGe for raised source/drains, new materials for capacitors, removal of high dose implanted resist, removal of small particles without adverse impact on structures, use of ceria-based slurries for chemical-mechanical polishing (CMP), needs for etching, cleaning and drying contacts and other structures with increasing aspect ratios, and the efforts in chemical and water usage reduction for ESH and COO benefits.
A particular apparatus used for wet cleaning semiconductor wafers is disclosed in U.S. Pat. No. 7,938,906, issued on May 10, 2011 to the inventor of the present application. The teaching of U.S. Pat. No. 7,938,906 is incorporated herein by reference.
U.S. Pat. No. 7,938,906 discloses an apparatus having a micro processing chamber in which a semiconductor wafer is closely received and processed. The micro processing chamber composed of an upper chamber and a lower chamber can be either situated in the open position to load or remove the semiconductor wafer or in the closed position to introduce chemical reagents or other fluids into the chamber for the processing of the semiconductor wafer. The above-mentioned open or closed position can be accomplished by the relative movement of the upper and lower movable parts.
In U.S. Pat. No. 7,938,906, the upper and lower movable parts of the apparatus are held together by four posts extending upwardly from each corner portion of the bottom plate of the lower movable part to the top plate of the upper movable part, along which the movable parts can be raised or lowered to set the micro processing chamber in the open or closed position. However, there are several problems associated with this design, thus the apparatus disclosed in U.S. Pat. No. 7,938,906 is not suitable for certain applications. First, the posts limit the three-dimensional movement of the micro processing chamber that is needed for certain applications. Second, when the chamber dimension is getting bigger, the plates that hold the upper chamber and lower chamber together can easily be deformed. The deformation will affect the shape and dimension of the internal space of the chamber formed after the upper chamber and lower chamber closed, resulting in unexpected processing results. Third, the prior art design requires accurate machining of the posts and corresponding holes in the plates and boxes in order to achieve a good alignment of all the parts. Finally, during the operation, the movable parts moving along the posts may produce particles caused by friction. The particles maybe the contamination source of the processing. In advanced semiconductor fabrication, it has been widely recognized that most particle contaminations come from the processing system. Therefore, there remains a need to optimize the apparatus design to simply the manufacture of components and to reduce contaminations resulting from the movement of the components of apparatus.